1. Field of the Invention
The invention relates to memory controllers used with computers, and more particularly to memory controllers providing address, row address strobe (RAS), column address strobe (CAS) and write enable signals to dynamic random access memories (DRAMS).
2. Description of the Related Art
Microprocessor-based computer systems have been increasing in performance at a tremendous rate. Much of this increase has been based on the improvements in the microprocessor itself. For example, clock speeds are reaching those previously used only by mainframe computers. However, affordable memory device performance has not been increasing at the same rate. Indeed, dynamic random access memory (DRAM) performance has flattened out recently, with the majority of the effort being concentrated on increasing device storage size. Thus main memory has become a bottleneck.
Cache memory systems, where a small amount of very fast, expensive static RAM is used to store copies of the data, have made the problem somewhat less severe, but the designs are very complicated and expensive. Further, the poor memory performance returns when access must be made to main memory. So there still is a need to improve the performance of the main memory system.
Page mode memory devices provide one way to increase memory system performance. If consecutive accesses are made to the same row address, referred to as the same page, only column addresses need be provided. This allows a dramatic reduction in cycle time for those cases, referred to as page hits. This is a quick gain and relatively easily made by itself, but more performance is always desired.
In many processors, the address is provided before the data portion of the cycle. This is referred to as pipelining and allows a performance increase in the memory systems. All of the address decoding can be started before the data portion begins, so that partially parallel operations can occur.
In most cases this overlap is somewhat minimal, one or two clock cycles, as the related systems cannot handle much more complexity. For example, the memory controller is conventionally built as a synchronous controller, based on a major state machine to control events and advancing on the processor clock edge. As the complexities of the microprocessor and the computer system increase, the conventional memory controller design becomes very limiting. It is exceedingly difficult to build a major state machine to handle all the possible cases. The complexity is daunting, if not overwhelming. As a result, numerous potential performance improvements have to be limited. Usually this means that any pipelining is limited and there are very few parallel operations. While some designs allowed write operations to be posted, this just further increased complexity in other ways. As a result, some other feature was sacrificed, so potential gains were lost.
Memory system performance is also a trade off between cost and speed. While conventionally 80 ns DRAMs have been used, 60 ns devices are available, though at a slightly higher cost. While prior memory controllers could utilize differing speeds of DRAMs, allowing the user to make the speed versus cost tradeoff, a mixed speed system did not obtain any benefits. The memory controller could use different speed DRAMs, but only one actual speed of operation was allowed in the system. The memory controller thus ran at the speed of the slowest of the installed DRAMs. This did not allow the user to have fast memory areas, such as the base memory area, and slow memory areas, such as extended memory locations in the main system memory controlled by the memory controller. This limitation arose again because of the complexities of memory controllers.
One further limitation to memory system design has been timing skew and propagation delay problems in providing the actual address, RAS, CAS, and write enable signals to the memory devices. For DRAMs the address is provided in two portions, the row address and the column address. These addresses are typically developed by multiplexing the addresses provided to the memory system. A row address strobe or RAS signal is provided with the row addresses, while a column address strobe or CAS signal is provided with the column addresses. The particular RAS and CAS signals provided to individual devices are generally prepared from master signals, referred to as MRAS and MCAS. The master signals have the desired timing information in relation to the addresses and data, but they must be qualified by other signals so that only the proper memory devices are activated. Generally this is done by doing bank selection encoding of the MRAS signal, so that only the memory devices having in the proper address range receive RAS signals. The MCAS signal is typically encoded with the signals relating to the particular byte or bytes of the full width which are active. In read cases this is usually the full width, but in write cases must be properly qualified so that erroneous data is not written. Similarly, a master write enable or MWE signal is used and provided to the devices. This signal can be provided to all of the devices as the CAS signal is providing the necessary chip enabling signal.
Conventionally the address multiplexing has been performed in one device along with master signal development, such as the memory controller chip itself, while the various additional qualifying has been done on other chips external to the memory controller chip. In fact, the qualification has generally been done asynchronously, while some of the other development has been done synchronously. One problem with this arrangement is that with all of these operations, the multiplexing, the master signal development, the further qualifications, and the mixed asynchronous and synchronous development, timing skews and propagation delays become significant and must be considered when any timing margin analysis is performed. Indeed, when working with the very high clock rates present in current microprocessor systems, the skews and delays can add an entire clock cycle to each memory cycle, thus degrading system performance.
Thus there are memory system performance gains that could be achieved, but conventional design limitations render them only potential, not practical. Therefore it is clearly desirable to have a memory controller which makes maximum use of processor address pipelining, can run numerous cycles concurrently in the greatest number of cases, can effectively use different speed memory devices and minimizes any timing related problems in providing the various signals to the memory devices.